This invention relates generally to an integrated memory device and, more specifically, to a method and apparatus for measuring threshold voltages associated with the EEPROM portion of a non-volatile DRAM (NVDRAM) memory cell.
An NVDRAM cell has been described in "A New Architecture for the NVRAM--An EEPROM Backed-Up Dynamic RAM", IEEE Journal of Solid State Circuits, Vol. 23, No. 1, February 1988; by Chuang et al. in U.S. Pat. No. 4,611,309; and in Yamauchi et al., "A Versatile Stacked Storage Capacitor on Flotox Cell for Megabit NVRAM Applications", from 1989 International Electron Devices Meeting Technical Digest, pages IEDM 89-595 through 598. These references are incorporated herein by reference.
A design related to that of the present invention is described in the article submitted herewith as Appendix A, entitled "A 256-bit Non-Volatile Dynamic RAM With ECC and Redundancy", by Fukumoto et al., which is incorporated herein by reference.
An NVDRAM cell includes a DRAM cell and an EEPROM cell. The DRAM cell, which typically consists of a MOS transistor in series with a storage capacitor, is volatile, while the EEPROM cell, which stores data in the form of charge on a floating gate in a floating gate MOS transistor, is non-volatile. The advantage of the NVDRAM is that while data may be quickly read from and written to the DRAM during normal operation, it can be stored in the non-volatile EEPROM during power down. The EEPROM data in an NVDRAM, however, is not directly accessible and must be transferred to the DRAM before being read.
An NVDRAM memory device, which includes a plurality of NVDRAM memory cells, has at least three operating modes: (1) a DRAM read/write mode in which the NVDRAM operates like a regular DRAM; (2) a store mode in which the DRAM data is transferred to the EEPROM to be stored; and (3) a recall mode in which the EEPROM data is transferred to the DRAM to be accessed.
In the DRAM read/write operating mode of an NVDRAM cell, the EEPROM transistor is turned off, and data is written to and read from the DRAM cell in the conventional manner--namely, the DRAM transistor is turned on when data is to be stored on or read from the DRAM storage capacitor, and otherwise is turned off.
When the DRAM data needs to be stored in the EEPROM, a store operation, which transfers the DRAM data to the EEPROM, is executed. The data is now stored as charge on the floating gate of the EEPROM transistor. When the EEPROM data needs to be recalled to the DRAM, a recall operation is executed. This operation consists of sensing the logic state of the EEPROM and, accordingly, charging a full logic state 1 or logic state 0 voltage level onto the DRAM storage capacitor.
In an integrated memory device, memory transistor threshold voltages are important indicators of the device's performance and reliability. A transistor's threshold voltage is the voltage at which the transistor starts conducting current after it has just been in a nonconducting state. The conducting and non-conducting states of a transistor, then, are associated with logic states 0 and 1, respectively, and the difference between the logic state 0 and logic state 1 thresholds is called the "window" of the transistor. A transistor with a smaller "window" is more likely to err as a result of random voltage swings, from noise, for instance, resulting in unintended logic swings. Hence, the size of this window is a measure of the memory transistor's reliability in differentiating signals corresponding to one logic state from those corresponding to the other.
In a floating gate EEPROM transistor, the threshold voltage may be "programmed" to different values by injecting different amounts of charge onto the floating gate. Thus, an excess of electrons on the floating gate of an EEPROM transistor, corresponding to a logic state of 1, causes a rise in the gate-to-source voltage necessary to turn on that transistor. Conversely, a lack of electrons on the floating gate, corresponding to a logic state of 0, results in a higher positive potential on the floating gate and a resulting decrease in the gate-to-source voltage necessary to turn on that transistor.
A transistor's window may vary over time. In floating gate EEPROM transistors, charge builds up over time, under normal operation, in the oxide region of the transistor--resulting in shrinkage of the window. Hence, the performance and reliability of an EEPROM memory transistor may be tracked over time by periodically measuring its logic state 0 and logic state 1 threshold voltages.
Transistors are typically biased to some normal operating point. If this operating point is too close to either the logic state 0 or logic state 1 threshold voltages, errors can occur from accidental turn-off or turn-on of transistors.
In addition, during normal operation, the EEPROM voltage is sensed, to determine its logic state, before it reaches its steady state threshold value. This means that a transistor's normal operating window, which is the difference between the actual EEPROM voltage when sensed as logic state 0 and that when sensed as logic state 1, is actually smaller than its total window as measured from its logic state 0 DC threshold to its logic state 1 DC threshold. Thus, measuring an EEPROM's gate-to-source voltages under normal biasing conditions provides information on the transistor's operating margin. The smaller the margin, the more likely it is that during normal operation, an EEPROM voltage, supposedly corresponding to a certain logic state, will be sensed as the opposite state.
Thus, it is desirable to know the threshold voltages of the memory transistors in a memory device in order both to provide for sufficient operating margins and to monitor the device's performance and reliability over time.
In a conventional EEPROM circuit (i.e. not in an NVDRAM), the EEPROM threshold voltage is easily determined, because the control gate of the EEPROM transistor is manipulable independently of the sensing circuitry which senses current through the EEPROM. First, the EEPROM may be programmed to either logic state 0 or logic state 1. Next, one node of the EEPROM transistor may be charged high in order to send current through the transistor. Then, the control gate voltage may be adjusted while monitoring current flow through the EEPROM. The control gate voltage at the point of current turn-off or turn-on is the threshold voltage programmed by the charge on the floating gate.
In an NVDRAM cell, however, the control gate of the EEPROM cell is tied to the source of the DRAM transistor. Since the operation of the sensing circuitry requires that the voltage at the source of the DRAM transistor be held at a certain level, and since the control gate of the EEPROM transistor is electrically tied to this level, it is not possible to independently manipulate the control gate voltage while, at the same time, enabling the sensing circuitry. Thus, the EEPROM threshold voltage may not be measured in the conventional manner.